As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular manufacturing facility. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. As line widths shrink smaller and smaller in submicron photolithography, the process to print lines and contact holes in photoresist becomes increasingly more difficult.
With circuit advancement to the ultra-large-scale integration (ULSI) levels, more and more layers are added to the surface of the wafer. These additional layers in turn create more steps on the wafer surface. The resolution of small image sizes in photolithography thus becomes more difficult over the additional steps because it becomes more difficult due to the increased problem of depth of focus. Planarization techniques become increasingly more important to offset the effects of a varied topography.
The formation of contact structures as transistor dimensions decrease is also important to predict and control device performance. A variety of contact structures have been considered to alleviate various problems such as contact resistance and the maximum area of devices available, such as the areas of source and drain regions, in order to make full contact to the devices with the contact structures. Self-aligned silicides are one alternative for alleviating contact area and resistivity problems associated with contacting source and drain regions. In addition, the self-aligned suicides make the diffused regions more conductive and lowers the sheet resistance of the diffused regions. This self-aligned process is shown with reference to FIGS. 1 and 2. After the transistor 14 is formed having gate oxide 16 and polysilicon or polycide gate electrode 18, the lightly doped drain (LDD) regions 22 are formed by conventional methods by implanting a light dose at the edge of the gate electrode near the channel to overcome such problems as hot-carrier effects. Sidewall oxide spacers 20 are formed along the edge of the gate electrode and gate oxide. The source/drain regions 24 are implanted with a heavier dose to form the source/drain junctions.
A metal 26 is deposited over the integrated circuit after which the wafer is heated. The silicon in the source/drain regions 24 then reacts with the metal 26 to form a suicide 28 as shown in FIG. 2. This process is called salicide if the silicide over the source/drain regions is formed at the same time as the silicide 30 over the polysilicon gate electrode. Everywhere there is silicon, the metal will react to form a silicide (the source/drain regions in area 28 and the polysilicon in region 30). Elsewhere the metal remains unreacted and is selectively removed. A dielectric layer is typically formed over the integrated circuit with contact openings formed to the source/drain regions and the polysilicon gate. The openings are generally filled with a metal to make contact to the silicide regions 28 and 30.
The refractory metals including titanium, tungsten, tantalum and cobalt have proven well-suited for use as the metal with which to form the silicide since the reaction with silicon occurs at relatively low processing temperatures, for example, 600.degree. C. or less. There are, however, disadvantages with this process of silicide formation. First, the silicide formation consumes a portion of the substrate silicon thus reducing the integrity of the source/drain regions. Second, titanium is commonly used for the silicide metal because of its low resistivity. However, during titanium disilicide formation, silicon tends to diffuse into the titanium which then may react over top of the sidewall oxide spacers. If silicide is formed over the oxide spacers it is continuous between the silicide formed over the polysilicon gate and the source/drain regions which will cause shorting between the gate electrode and the source/drain regions.
It is therefore an object of the present invention to provide a method of forming a planarized transistor having raised source and drain regions.
It is a further object of the present invention to provide such a method of forming the planarized transistors with raised source and drain regions with reduced resistivity.
It is a further object of the present invention to provide such a method of forming the raised source and drain regions in a manner which reduces junction leakage and reduces shorting between the gate and source/drain regions.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.